The increasing popularity of the field programmable gate array (FPGA) technology has generated a great deal of interest in the algorithmic study and tool development for FPGA specific design automation problems. The most widely used FPGAs are LUT based FPGAs, in which the basic logic element is a k-input lookup table (LUT) that can implement any Boolean function of up to k variables. This unique feature of the LUT has brought new challenges to technology mapping. This book studies the technology mapping problem for LUT-based FPGAs. According to the experimental results, the proposed algorithm generates favorable results for various FPGA architectures.